Open-Source RISC-V Cores: Analysis Of Scalar and Superscalar Architectures And Out-Of-Order Machines

A new technical paper titled “Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution” was published by researchers at ETH Zurich, Università di …

Full story: https://semiengineering.com/open-source-risc-v-cores-analysis-of-scalar-and-superscalar-architectures-and-out-of-order-machines/